1. Field of the Invention
The present disclosure is directed to a variable resistance memory device and method of manufacturing the same.
2. Description of the Related Art
With an ever-increasing demand for reduction of the power consumption of memory devices, research has been conducted on next-generation memory devices that are nonvolatile and do not need a refresh operation. Examples of next-generation memory devices that are nonvolatile and do not need a refresh operation include phase change random access memory (PRAM) devices using phase change materials, resistive random access memory (RRAM) devices using variable resistance materials such as transition metal oxides, and magnetic random access memory (MRAM) devices using ferromagnetic materials. The materials of next-generation memory devices such as PRAM, RRAM, and MRAM devices have a resistance that varies according to a current or voltage applied thereto and maintain a uniform resistance even after the current or voltage is cut off. In other words, since next-generation memory devices such as PRAM, RRAM, and MRAM devices have nonvolatile properties, they do not need a refresh operation.
FIG. 1 is a circuit diagram of a memory cell 10 of a typical next-generation memory device.
Referring to FIG. 1, the memory cell 10 includes a variable resistance device 11 and a switching device 12.
The variable resistance device 11 is connected between a bit line BL and the switching device 12, and the switching device 12 is connected between the variable resistance device 11 and a word line WL.
A next-generation memory device including the memory cell 10 may be classified as being a PRAM, RRAM, or MRAM device according to the type of the variable resistance device 11. In other words, if the next-generation memory device including the memory cell 10 is a PRAM device, then the variable resistance device 11 may be formed of a material whose resistance varies according to temperature, such as Ge—Sb—Te (GST). If the next-generation memory device including the memory cell 10 is an RRAM device, then the variable resistance device 11 may be formed of a transition metal oxide and may be interposed between an upper electrode and a lower electrode. If the next-generation memory device including the memory cell 10 is an MRAM device, then the variable resistance device 11 may be comprised of an insulator that is interposed between upper and lower electrodes of a magnetic material.
PRAM cells are disclosed in U.S. Pat. No. 6,760,017, RRAM cells are disclosed in U.S. Pat. No. 6,753,561, and MRAM cells are disclosed in U.S. Pat. No. 6,724,674.
In the meantime, as the demand for increasing the storage capacity of a memory device increases, the size of memory chips has gradually increased. Accordingly, the resistance, the parasitic resistance, and the capacitance of each signal line in a memory device increase, thereby imposing restrictions on the memory device's ability to perform operations at high speed. In order to address this challenge, methods of forming a hierarchy of signal lines have been applied to typical DRAM devices, and an example of these methods is disclosed in U.S. Pat. No. 6,069,815.
In order to increase the storage capacity and operating speed of next-generation memory devices that use variable resistance materials, signal lines must be formed hierarchically. Therefore, it is desirable to develop a new hierarchical layout of signal lines for variable resistance memory cells, in which each variable resistance memory cell is comprised of a variable resistance device and a switching device.